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type package tle 7469 gv52 pg-dso-12 tle 7469 gv53 pg-dso-12 dual low drop voltage regulator tle 7469 data sheet 1 rev. 1.6, 2008-01-22 features ? dual output 5 v ( 2%), 215ma and 2.6 v 1) ( 4%), 200ma or 5 v ( 2%), 215ma and 3.3 v ( 3%), 200ma ultra low quiescent cu rrent consumption < 55 a inhibit function very low dropout voltage reset with power-on delay early warning comparator window watchdog power sequencing for dual voltage c output protected against short circuit wide operation range: up to 45 v wide temperature range: -40 c to 150 c overtemperature protection overload protection green product (rohs compliant) aec qualified functional description the tle 7469 is a monolithic integrated vo ltage regulator with two voltage outputs specially designed to supply microcontr ollers with dual supply voltage: 2.6 v 1) or 3.3 v core and 5 v i/o voltage like the infineon xc 164 and xc161. 1) 2.5 v nominal specific ation range of most cs is compatible with the 2. 6 v output voltage range of the tle 7469.
data sheet 2 rev. 1.6, 2008-01-22 tle 7469 the voltage regulator features an integrated reset circui try which monitors the 2.6 v/ 3.3 v supply voltage. at po wer on the reset che cks both supply voltages and performs the power-on reset with an ad justable delay time. the volta ge difference is kept in the range -0.5 v < ( v q1 - v q2 ) < 3.0 v even during power-on and power-down time enabling save c operation without extern al clamping. using the in tegrated early warning comparator an external voltage can be supe rvised. an integrated output sink current circuitry keeps the voltage at the q1 pin below 5.5 v even when reverse currents are applied. thus connected devi ces are protected from overvo ltage damage. the regulator can be shut down via the inhi bit input causing th e current consumpt ion to drop below 9 a. the tle 7469 is designed for use under the severe conditions of automotive applications, and is therefore equipped with protection func tions against overload, short circuit and overtemperature. it operates in the wide junction temperature range from -40 c to 150 c and offers the low quiescent curre nt consumption required for body applications. for applications requiring extr emely low noise levels the in fineon voltage re gulator family tle 42xy and tle 44xy is mo re suited than the tle 7469 . a mv-range output noise on the tle 7469 caused by th e charge pump operation is una voidable due to the ultra low quiescent current concept.
tle 7469 data sheet 3 rev. 1.6, 2008-01-22 figure 1 block diagram tle 7469 overtemperature shutdown 1 overtemperature shutdown 1 bandgap reference charge pump inhibit inh 2 i2 12 si 8 i1 1 reset generator and window watchdog q2 ro wdi dt 10 9 5 7 early warning so 4 q1 3 11 gnd aeb03530_1.vsd charge pump q1
data sheet 4 rev. 1.6, 2008-01-22 tle 7469 t figure 2 pin configuration (top view) table 1 pin definitions and functions pin no. symb. function 1i1 input voltage 1; block to ground directly at the ic with a 100 nf ceramic capacitor 2inh inhibit input; low level disables the ic. integrated pull-down resistor 3q1 output voltage 1; 5.0 v, block to gnd with a capacitor c q1 1 f, esr < 6 ? at 10 khz 4so sense output; output of early warning comparator, open collector output 5wdi watchdog input; trigger input fo r watchdog pulses 6, 11 gnd ground; pin 6, 11 and heat slug must be connected to gnd 7dt dt delay timing; connect to gnd, q1 or q2 to select reset and watchdog timing 8si sense input; input for early warning comparator 9ro reset output; open collector output with integrated 20 k ? pull-up resistor 10 q2 output voltage 2; 2.6 v (tle 7469 gv52), 3.3 v (tle 7469 gv53); block to gnd with a capacitor c q2 1 f, esr < 6 ? at 10 khz 12 i2 input voltage 2; block to ground directly at the ic with a 100 nf ceramic capacitor aep03531.vsd 1 i1 2 inh 3 q1 12 11 10 gnd q2 4 so 5 wdi 6 gnd 9 8 7 ro si dt i2 pg-dso-12
tle 7469 data sheet 5 rev. 1.6, 2008-01-22 table 2 absolute maximum ratings -40 c < t j < 150 c parameter symbol limit values unit remarks min. max. input i1 voltage v i1 -0.3 45 v ? current i i1 ? ? ma internally limited input i2 voltage v i2 -0.3 45 v ? current i i2 ? ? ma internally limited output q1 voltage v q1 -0.3 5.5 v permanent voltage v q1 -0.3 6.2 v t < 10 s 1) current i q1 ? 2 ma internally limited output q2 voltage v q2 -0.3 5.5 v permanent voltage v q2 -0.3 6.2 v t < 10 s 1) current i q2 ? ? ma internally limited inhibit input inh voltage v inh -0.3 45 v observe current limit i inh max 2) current i inh -1 1 ma ? reset output ro voltage v ro -0.3 5.5 v permanent voltage v ro -0.3 6.2 v t < 10 s 1) current i ro ? ? ma internally limited delay timing dt voltage v dt -0.3 5.5 v permanent voltage v dt -0.3 6.2 v t < 10 s 1) current i dt -5 5 ma ?
data sheet 6 rev. 1.6, 2008-01-22 tle 7469 note: maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. inte grated protection functions are designed to prevent ic destruction under fault condit ions. fault conditions are considered as outside no rmal operating range. prot ections functions are not designed for continuous repetitive operation. watchdog input wdi voltage v wdi -0.3 5.5 v permanent voltage v wdi -0.3 6.2 v t < 10 s 1) current i wdi ? ? ma internally limited sense input si voltage v si -0.3 45 v observe current limit i simax 2) current i si -1 1 ma ? sense output so voltage v so -0.3 5.5 v permanent voltage v so -0.3 6.2 v t < 10 s 1) current i so ? ? ma internally limited temperatures junction temperature t j ?150 c? storage temperature t stg -50 150 c? 1) exposure to these absolute maxi mum ratings for extended periods ( t > 10 s) may affect device reliability. 2) external resistor required to keep current below absolute maximum rating when voltages 5.5 v are applied. table 2 absolute maximum ratings (cont?d) -40 c < t j < 150 c parameter symbol limit values unit remarks min. max.
tle 7469 data sheet 7 rev. 1.6, 2008-01-22 note: in the operating range th e functions given in the circ uit description are fulfilled. table 3 operating range parameter symbol limit values unit remarks min. max. input voltage v i1 5.6 45 v ? input voltage v i2 6.0 45 v v i1 > 8v input voltage v i2 4.2 45 v v i1 < 8v junction temperature t j -40 150 c? thermal resistances pg-dso-12 junction case r thjc ?4.4k/w? junction ambient r thj-a ? 107 k/w pcb, only footprint 1) junction ambient r thj-a ? 58 k/w pcb heat sink area 300 mm 2 1) junction ambient r thj-a ? 48 k/w pcb heat sink area 600 mm 2 1) 1) package mounted on pcb 80 80 1.5 mm 3 ; 35 cu; 5 sn; zero airflow; 85 c ambient temperature.
data sheet 8 rev. 1.6, 2008-01-22 tle 7469 table 4 electrical characteristics v i1 = 13.5 v; v i2 = 13.5 v; -40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max. output q1 output voltage v q1 4.90 5.0 5.10 v 1 ma < i q1 < 215 ma, 6 v < v i1 < 16 v output current limitation i q1 320 ? 700 ma v q1 = 4.0 v output drop voltage; v drq1 = v i1 - v q1 v drq1 ? 300 600 mv i q1 = 215 ma 1) load regulation ? v q1,lo ?2560mv1 ma < i q1 < 215 ma line regulation ? v q1,li ?2050mv i q1 = 1 ma, 10 v < v i < 28 v power supply ripple rejection psrr ?60? db f r = 100 hz, v r = 1 vpp reverse output current protection v q,rev ??5.5v i q,rev = 1 ma, v inh = 0 v output q2 output voltage v q2 2.50 2.60 2.70 v 1 ma < i q2 < 200 ma, 6 v < v i2 < 16 v, tle 7469 gv52 output voltage v q2 3.20 3.30 3.40 v 1 ma < i q2 < 200 ma, 6 v < v i2 < 16 v, tle 7469 gv53 absolute differential voltage v q1 - v q2 -0.5 ? 3.0 v v q1 , v q2 > 1 v output current limitation i q2 300 ? 550 ma v q2 = 2.0 v load regulation ? v q2,lo ?2560mv1 ma < i q2 < 200 ma line regulation ? v q22,li ?2050mv i q2 = 1 ma, 10 v < v i < 28 v power supply ripple rejection psrr ?60? db f r = 100 hz, v r = 1 vpp
tle 7469 data sheet 9 rev. 1.6, 2008-01-22 current consumption quiescent current; i q = i i1 + i i2 - i q1 - i q2 i q ??55 a i q2 = i q1 = 100 a, t j < 80 c quiescent current; inhibited i q ?59 a v inh = 0 v, t j < 80 c inhibit input inh turn-on voltage v inh on ??3.1v v q1 & v q2 on turn-off voltage v inh off 0.8 ? ? v v q1 & v q2 off h-input current i inh on ?34 a v inh = 5 v l-input current i inh off ?0.51 a v inh = 0 v, t j < 80 c delay timing dt threshold fast timing select v dt,fast 4.5 ? ? v ? threshold slow timing select v dt,slow 2.3 ? 3.3 v tle 7469 gv52 threshold slow timing select v dt,slow 2.3 ? 3.6 v tle 7469 gv53 threshold watchdog turn off 2) v dt,off ??0.8v? watchdog input wdi h-input voltage threshold v wdih ??3.0v? l-input voltage threshold v wdil ??0.8v? watchdog sampling time t sam 0.20 0.25 0.30 ms fast timing 0.80 1.00 1.20 ms slow timing ignore window time t ow 25.6 32.0 38.4 ms fast timing 102 128 154 ms slow timing open window time t ow 25.6 32.0 38.4 ms fast timing 102 128 154 ms slow timing table 4 electrical characteristics (cont?d) v i1 = 13.5 v; v i2 = 13.5 v; -40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
data sheet 10 rev. 1.6, 2008-01-22 tle 7469 closed window time t cw 25.6 32.0 38.4 ms fast timing 102 128 154 ms slow timing window watchdog trigger time t wd 39.0 44.8 50.6 ms fast timing 156 179 202 ms slow timing reset output ro reset switching threshold 2 v rt2 2.35 2.38 2.48 v tle 7469 gv52, v q2 decreasing reset headroom 2 v rh2 130 190 mv tle 7469 gv52 reset switching threshold 2 v rt2 3.00 3.07 3.15 v tle 7469 gv53, v q2 decreasing reset headroom 2 v rh2 165 240 mv tle 7469 gv53 reset hysteresis 2 v rh2 ? 45 ? mv tle 7469 gv52 3) ? 60 ? mv tle 7469 gv53 4) reset switching threshold 1 v rt1 4.50 4.65 4.80 v v q1 decreasing reset hysteresis 1 v rh1 ?90? mv? reset sink current i ro ??1 ma v q = 5 v, v ro = 0.5 v reset output low voltage v rol ?0.150.25v v q2 1 v reset high voltage v roh 4.5 ? ? v ? integrated reset pull- up resistor r ro 10 20 40 k ? internally connected to q1 power-up reset delay time t rd 6.0 8.0 10.0 ms fast timing ( v dt 4.5 v) 24.0 32.0 40 ms slow timing ( v dt 3.3 v) reset reaction time t rr ?1026 s? table 4 electrical characteristics (cont?d) v i1 = 13.5 v; v i2 = 13.5 v; -40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
tle 7469 data sheet 11 rev. 1.6, 2008-01-22 input voltage sense sense threshold high v sih 1.10 1.16 1.22 v v si increasing (see figure 4 ) sense threshold low v sil 1.06 1.12 1.18 v v si decreasing (see figure 4 ) sense output low voltage v sol ?0.10.4v v si < 1.01 v; v i1 > 4.20 v; i so = 0.5 ma external so pull-up resistor r so ext 9.2 ? ? k ? v q1 = 5v sense input current i si - 10.11 a v si = 5 v sense high reaction time t pd so lh ?4.0? s? sense low reaction time t pd so hl ?4.0? s? 1) measured when the output voltage has dropped 100 mv from the nominal value obtained at v i1 = 13.5 v, v i2 = 13.5 v. 2) watchdog off, reset in slow mode. 3) specified by design, not subject of production test. 4) specified by design, not subject of production test. table 4 electrical characteristics (cont?d) v i1 = 13.5 v; v i2 = 13.5 v; -40 c < t j < 150 c; unless otherwise specified parameter symbol limit values unit test condition min. typ. max.
data sheet 12 rev. 1.6, 2008-01-22 tle 7469 application information figure 3 application diagram with typical external components a typical application of the tle 7469 is shown in figure 3 . to prevent the regulation loop from oscillating a ceramic capacitor of c q1/2 1 f is required at ea ch of the outputs q1 and q2. in contrast to most low drop voltage regula tors the tle 7469 only needs moderate capacitance at the outputs and tolerates cerami c capacitors to keep the stability. this offers more design flexibilit y to the circuit designer enabling the ic also to operate without ta ntalum capacitors. additional a buffer capacitor c b of > 10 f should be used for each output q1 and q2 to suppress influences from load surges to th e voltage levels. this one can either be an aluminum electrolytic capacitor or a t antalum capacitor following the application requirements. a general recommendation is to keep the drop over the equiva lent serial resistor (esr) together with the discharge of the blocki ng capacitor below the reset headroom (e.g. min. 130mv for the 2.6v output). aea03529_2.vsd tle 7469 q2 dt wdi ro so q1 xc 164 1 f 47 f 10 k ? 1 f 47 f 100 nf r vi * 100 k ? i2 inh si 100 nf v bat 47 f e. g. ignition key i1 gnd = optional
tle 7469 data sheet 13 rev. 1.6, 2008-01-22 since the regulator output curr ent roughly rises linearly with time the discharge of the capacitor can be calc ulated as follows: dvc b = di q *dt/c b the drop across the esr calculates as: dv esr = di*esr to prevent a reset the following relationship must be fullfilled: dv c + dv esr < v rh2 = 130mv example: assuming a load current step of di q = 50ma, a blocking capacitor of c q = 22f and a typical regulator reaction time under normal operati ng conditions of dt ~ 25s and for special dynamic load conditions, such as load step from very low base load, a reaction ti me of dt ~ 75s. dv c = di q *dt/c b = 50ma * 25s/22f = 54mv so for the esr we can allow dv esr = v rh2 - dv c = 130mv - 54mv = 76mv the permissible esr becomes: esr = dv esr / di q = 76mv/50ma = 1.52ohm during design-in of the TLE7469 product family, special ca re needs to be taken with regards to the regulators reac tion time to sudden load curr ent changes starting from very low pre-load as well as cyclic lo ad changes. the appl ication note ? tle7x voltage regulators - application note about transi ent response at ultra low quiescent current voltage regulators ? (see 3_cip05405.pdf) gi ves important hints fo r successful design-in of the voltage regulators of the tle7x family. as a dual regulator the tle 7469 for correct operation shou ld be always supplied at both input pins i1 and i2 out of one voltage supply. the dual voltage regulato r with both inputs accessible, offers the possibility to reduce the power di ssipation in the package. this can be achived by two different inpu t voltages or a drop resistor* r vi (see figure 3 ) at the input pin i2 for the 2.6v output. if one of this options is chosen,care should be taken, to apply the device as descibed unde r ?table 3: operating range?. the reset output ro features an integrated pull-up resist or. thus it can be directly coupled to the microc ontroller reset input.
data sheet 14 rev. 1.6, 2008-01-22 tle 7469 the sense comparator output so is an open collector. an appropriate external pull-up resistor is typ. 5.6 k ? ? 47 k ? , the minimum value of 5.6 k ? being defined by the max. sink current capability of th e so output transistor. if th e sense comparator is not used the pull-up resistor can be spar ed. in this case the si pin should be directly connected to q1 in order to keep th e comparator inactive. figure 4 sense timing diagram aed02559_7469 t sense t sih v sil v input voltage high low output sense t pd so lh pd so hl t
tle 7469 data sheet 15 rev. 1.6, 2008-01-22 circuit description power on reset in order to avoid any system failure, a sequence of several conditions has to be passed. when the level of v q2 reaches the reset threshold v rt , the signal at ro remains low for the power-up re set delay time t rd . then a second comp arator checks whether v q1 v rt1 and only if this test is passed the reset output is switched to high. the reset output is only released (set to high level) if both output voltages have passed their specific reset threshold v rt1/2 . the reset functi on and timing is illustrated in figure 5 . the reset reaction time t rr avoids wrong triggering caused by short ?glitches? on the v q2 -line. for power-fai l, in case of v q2 or v q1 power down ( v q2 < v rt2 or v q1 < v rt1 for t >t rr ) a logic low signal is generated at the pin ro to reset an external microcontroller.
data sheet 16 rev. 1.6, 2008-01-22 tle 7469 figure 5 reset function and timing diagram watchdog operation the watchdog uses a fraction of the charge pump oscillator?s clock signal as timebase. connecting the dt pin to q1 or to q2 the watchdog ti mebase can be adjusted. the watchdog can be turned off by a low level ( v dt 0.8 v) applied to th e dt pin. the timing values used in this text re fer to typ. values with dt connected to q1 (fast timing). figure 6 shows the state diagram of the window watchdog ( wwd). after power-on, the reset output signal at the ro pin (microcontroller re set) is kept low for the reset delay time t rd of typ. 8 ms. with the low to high transition of the signal at ro the device starts the ignore window time t cw (32 ms). during th is window the signal at the wdi pin is ignored. next the wwd star ts the open window. when a va lid trigger signa l is detected during the open window a closed window is initialized immedi ately. a trigger signal within v i t aet03532.vsd v q1 t v rt1 v q2 t v rt2 v ro t v rol v roh t rd t rd t rd t rr t rr
tle 7469 data sheet 17 rev. 1.6, 2008-01-22 the closed window is interprete d as a pretrigger failure and results in a reset. after the closed window the open wi ndow with the duration t ow is started again. the open window lasts at minimum until the trigger process has occurred, at maximum t ow is 32 ms (typ. value with fa st timing). a high to low transition of the watchdog trigger si gnal on pin wdi is taken as a trigger. to avoid wrong triggering due to parasitic glitches two h igh samples followed by two low samples (sample period t sam typ. 0.25 ms) are decoded as a valid trigger (see figure 8 ). a reset is generated (ro goes low) if there is no trigger pulse during the open window or if a pretrigger occurs duri ng the closed window. the triggering is correct also, if the first three samples (two high on e low) of the trigger pulse at pin wdi are inside the closed window and only the fourth sample (t he second low sa mple) is taken in the open window. figure 6 window watchdog state diagram aea03533.vsd no trigger closed window open window trigger reset ignore window always always no trigger during open window trigger during closed window
data sheet 18 rev. 1.6, 2008-01-22 tle 7469 figure 7 window watchdog signal flow figure 8 window watchdog definitions t vi/v vq/v vro/v wnd wdi/v t rd ingnore wnd v rt 1. correct trigger no trigger in ow t rr t t t t ow cw t rr cw (wrong) trigger in cw t wd,p t rd power fail t rd ow cw normal operation don?t care wdi during iw ow ow ow aet02952 watchdog trigger signal valid not valid = watchdog decoder sample point ecw t closed window wdi wdi open window eow t open window closed window
tle 7469 data sheet 19 rev. 1.6, 2008-01-22 package outlines figure 9 pg-dso-12 (plastic green d ual small outline) green product (rohs compliant) to meet the world-wi de customer requirements for envi ronmentally friendly products and to be compliant with government regula tions the device is available as a green product. green products are ro hs-compliant (i.e pb-free fi nish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gps09628 1) does not include plastic or metal protrusion of 0.15 max. per side (heatslug) standoff index marking 1 12 2.6 max. 7.8 (body) 2.35 0.1 0 +0.1 (4.4 mold) 6 (mold) 7 6 1 7 12 0.8 0.1 (1.55) 0.25 5? 3? heatslug (metal) 0.1 10.3 0.3 0.25 b 7.5 0.1 1) b +0.075 -0.035 7.6 +0.13 -0.1 0.7 0.15 b 6.4 0.1 1) +0.13 0.4 0.25 m a c b 12x 1 5 x = 5 (1.8 mold) 0.1 1.6 0.1 (metal) 4.2 (metal) 5.1 0.1 1 bottom view for further packge information, please visit our website: http://www.infineon.com/packages. dimensions in mm
data sheet 20 rev. 1.6, 2008-01-22 tle 7469 revision history version date changes rev. 1.6 2008-01-22 initial version of rohs-compliant derivate of tle 7469 page 1 : aec certified statement added. page 1 and page 19 : rohs compliance statement and green product feature added. page 1 and page 19 : package changed to rohs compliant version. rev. 1.5 2007-05-07 modifications according to pcn no. 2007-070-a page 8: parameter ?out put current limitation i q2 ? : max. value modified from 500ma to 550ma. page 3, fig. 1 modified: ro pullup to q1 instead to q2. legal disclai mer updated. rev. 1.4 2005-07-15 final datasheet
edition 2008-01-22 published by infineon technologies ag 81726 munich, germany ? 2008 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical valu es stated herein and/or any information regarding the application of the device, infineon technologies her eby disclaims any and all warranties and liabilities of any kind, including wi thout limitation, warranties of non-infrin gement of intellectual property rights of any third party. information for further information on technology, delivery terms an d conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the near est infineon technologies office. infineon technologies components may be used in life-supp ort devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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